1. Field of the Invention
The present invention relates to synchronous type semiconductor memory devices and more particularly to a synchronous type semiconductor memory device operating in synchronization with a clock signal.
2. Description of the Background Art
FIG. 22 is a block diagram showing the configuration of a conventional synchronous random access memory (hereinafter referred to as an SDRAM 70). Referring to FIG. 22, SDRAM 70 includes a clock buffer 71, a control signal input circuit 72, an address input circuit 73, a mode register 74, and a control circuit 75.
Clock buffer 71 is activated by a signal CKE and it transmits an external control signal CLK to control signal input circuit 72, address input circuit 73, and control circuit 75. Control signal input circuit 72 latches and supplies external control signals /CS, /RAS, /CAS, /WE, DQM to control circuit 75 in synchronization with external clock signal CLK from clock buffer 71. Address input circuit 73 latches and supplies external address signals A0 to Am (m is an integer of at least 0) and a bank selection signal BA to control circuit 75 in synchronization with external clock signal CLK from clock buffer 71. Mode register 74 stores modes designated by external address signals A0 to Am, for example. Control circuit 75 produces various internal signals in accordance with signals from clock buffer 71, input circuits 72, 73 and mode register 74, and controls the entire SDRAM 70.
SDRAM 70 includes a memory array 76a (bank #0), a memory array 76b (bank #1), row decoders 77a, 77b, column decoders 78a, 78b, sense amplifier+input/output control circuits 79a, 79b, a data transfer circuit 80, a data input/output circuit 81.
Memory array 76a is arranged in a matrix and it includes a plurality of memory cells each storing 1-bit data. Each memory cell is arranged at a prescribed address determined by row and column addresses.
Row decoder 77a designates row addresses of memory array 76a in response to row address signals RA0 to RAm supplied from control circuit 75. Column decoder 78a designates column addresses of memory array 76a in response to column address signals CA0 to CAm supplied from control circuit 75.
Sense amplifier+input/output control circuit 79a connects memory cells at addresses designated by row decoder 77a and column decoder 78a to one end of a data bus DB. Memory arrays 76a and 76b, row decoders 77a and 77b, column decoders 78a and 78b, sense amplifier+input/output control circuits 79a and 79b have respective same configurations.
The other end of data base DB is connected to data transfer circuit 80. ata transfer circuit 80 is controlled by control signals .PHI.1, .PHI.2, . . . supplied from control circuit 75 and it transfers data between data bus DB and data input/output circuit 81. Data input/output circuit 81 is controlled by control signals .PHI.3, . . . supplied from control circuit 75, and it supplies externally input data through data transfer circuit 80 and data bus DB to a selected memory cell in a writing mode, and externally outputs read data that is read from a selected memory cell and supplied through data bus DB and data transfer circuit 80 in a reading mode.
FIG. 23 is a circuit block diagram showing a portion that is related to transfer and output of read data DO of SDRAM 70 shown in FIG. 22. Referring to FIG. 23, SDRAM 70 is provided with a DLL circuit 82, a memory control circuit 83, a transfer control circuit 84, a preamplifier 85, latch circuits LA1 to LA3, and an output buffer 86.
DLL circuit 82, memory control circuit 83 and transfer control circuit 84 is included in control circuit 75 in FIG. 22. DLL circuit 82 produces an internal clock signal CLK' in synchronization with external clock signal CLK externally supplied through clock buffer 71. Memory control circuit 83 produces a preamplifier activation signal PAE in synchronization with external clock signal CLK, and supplies signal PAE to preamplifier 85. Transfer control circuit 84 produces transfer control signal .PHI.1 to .PHI.3 in synchronization with internal clock signal CLK' produced in DLL circuit 82, and supplies signals .PHI.1 to .PHI.3 to latch circuits LA1 to LA3, respectively.
Preamplifier 85 is provided at the last stage of each of sense amplifier+input/output control circuits 79a, 79b in FIG. 22. Preamplifier 85 is activated by signal PAE supplied from memory control circuit 83, and preamplifier 85 amplifies data DO read from a memory cell and supplies the data to one end of a data bus DB1.
The other end of data bus DB1 is connected through a latch circuit LA1, a data bus DB2, a latch circuit LA2, a data bus DB3, a latch circuit LA3 and an output buffer 86 to a data input/output pin DQP. Latch circuits LA1, LA2 are included in data transfer circuit 80 in FIG. 22, and latch circuit LA3 and output buffer 86 are included in data input/output circuit 81 in FIG. 22.
Latch circuit LA1 includes clocked inverters 91, 92, and inverters 93, 94. Clocked inverter 91 and inverter 93 are connected in series between data buses DB1 and DB2, and clocked inverter 92 and inverter 93 are reversely connected in parallel. Transfer control circuit .PHI.1 is directly input to the control node of clocked inverter 91 and input through inverter 94 to the control node of clocked inverter 92.
As shown in FIGS. 24A and 24B, clocked inverter 91 includes an input node 91a, an output node 91b, a control node 91c, P channel MOS transistors 95, 96, N channel MOS transistors 97, 98, and an inverter 99. P channel MOS transistors 95, 96 are connected in series between a power supply potential VDD line and output node 91b, and N channel MOS transistors 97, 98 are connected in series between output node 91b and a ground potential GND line. MOS transistors 96, 97 have their gates connected to input node 91a, and N channel MOS transistor 98 has its gate connected to control node 91c. Inverter 99 is connected between the gate of N channel MOS transistor 98 and the gate of P channel MOS transistor 95. When control node 91c attains an "H" level active state, MOS transistor 95, 98 are rendered conductive, and clocked inverter 91 operates as an inverter formed of MOS transistors 96, 97. This applies to clocked inverter 92.
Accordingly, in latch circuit LA1, while signal .PHI.1 is at an H level, clocked inverter 91 is activated, clocked inverter 92 is inactivated, and data signal on data bus DB1 is transmitted through clocked inverter 91 and inverter 93 to data bus DB2. While signal .PHI.1 is at an L level, clocked inverter 91 is inactivated, clocked inverter 92 is activated, data buses DB1 and DB2 are disconnected, and data signal on data bus DB2 is latched by inverter 93 and clocked inverter 92.
Latch circuits LA2, LA3 operate similarly to latch circuit LA1. While signal .PHI.2 is at an H level, data signal on data bus DB2 is transmitted through latch circuit LA2 to data bus DB3. While signal .PHI.2 is at an L level, data buses DB2 and DB3 are disconnected, and data signal on data bus DB3 is latched by latch circuit LA2. While signal .PHI.3 is at an H level, data signal on data bus DB3 is transmitted through latch circuit LA3 to output buffer 86. While signal .PHI.3 is at an L level, data bus DB3 and output buffer 86 are disconnected, and an input signal of output buffer 86 is latched by latch circuit LA3.
Output buffer 86 externally outputs data signal that is supplied from latch circuit LA3 through data input/output pin DQP.
FIG. 25 is a time chart showing the operation of the circuits shown in FIGS. 23, 24A and 24B. Referring to FIG. 25, DLL circuit 82 produces internal clock signal CLK' of which rising/falling timing is made earlier by predetermined time at the same frequency as external clock signal CLK.
After reading time Tout from the rising edge of external clock signal CLK in a certain cycle 0, read data DO is output to data bus DB1. In response to the rising edge of internal clock signal CLK' in cycle 1' that corresponds to the rising edge of external clock signal CLK in cycle 1, transfer control signal .PHI.1 attains an H level in a pulse manner, and data DO on data bus DB1 is accordingly transmitted through latch circuit LA1 to data bus DB2.
Similarly, pulses of transfer control signals .PHI.2, .PHI.3 attain an H level in a pulse manner in response to the rising edges of internal clock signal CLK' in cycles 2', 3', and read data DO is output to input/output pin DQP after prescribed time since the rising edge of internal clock signal CLK' in cycle 3'. Users of SDRAM 70 receive data DQ at this timing.
In such SDRAM 70, the acceptable frequency range of external clock signal CLK is predetermined for each chip. If a user tries to shorten the reading time, however, external clock signal CLK at a frequency higher than the acceptable range may be used.
In this case, transfer control signal .PHI.1 attains an H level in a pulse manner before data DO is output to data bus DB1 as shown in FIG. 26. Thus, read data DO cannot properly be received to latch circuit LA1 and a malfunction is caused.
Even if the frequency of external clock signal CLK is within the acceptable range, read data DO cannot properly be received to latch circuit LA1 and a malfunction is caused when reading time Tout becomes longer because of the using condition and over-time change of a chip.